A RDS v2.0 Design
The The extra carriers fit into the space 57KHz to 76KHz. The obligatory carrier is at 57KHz, the other carriers are optional as per requirements of the broadcaster.
The Block Diagram
The Building Blocks
The ADUAU1979 is a 192K dual channel ADC (use at 48KHz for simplified filters) for the L, R audio channels. The AES/EBU reciever and sample rate convertor incorporated in the DSP can be used for a digital input.
The DSP is an ADSP21562 32 bit Sharc processor with code compatibility with the ADSP21161 used for the stereo generator.
The DAC for the MPX is an AD1955 dual 192K device.
The 32 bit microcontroller should be a RISC processor with spi, UART, Ethernet + IP stack, flash, sufficient internal RAM. The micro will contain the DSP image in flash and boot the DSP via SPI, a second SPI is used to DMA the RDS frame parameters directly in the DSP data RAM. A UECP serial port and IP driven Ethernet port are for RDS parameters stored in flash. Likewise the DMA can be used to update the compression filter variables for dynamic program content optimisation.