Possible RDS v2.0 Project

Here we look at a possible RDS v2.0 encoder based upon the previously designs for the stereo encoder and RDS encoder. The generatiosn nod DSP pos-ADSP21161 have more than sufficient power to combine a stereo encoder and RDS encoder.

RDS 2.0

RDS 2.0 is the new super RDS, more throughput, new features, graphics, user prototypes etc... But compatibility with RDS 1.0 is maintained.

First, extra throughput is obtained by adding more carriers. After all if the bandwidth was just increase (the simple way) then compatibility with RDS 1.0 would be lost. So what is done, the same carrier structure, modulation etc. is kept but shifted to other frequencies. Three extra frequencies are defined above 57KHz, in the 19KHz band between 57KHz to 76KHz. (Specifically 66.5KHz, 71.25KHz, 76KHz). (MPX Spectrum)

The maximum multiple for generation of the carries has to be a multiple of 250Hz becuase of the additional RDS carriers. In the case of the non-RDS stereo encoder this was 1KHz. This means the number of samples for a 192KHz mpx sample rate is: 768. It wouyld be better to have a higher MPX re-construction sample rate but there are still no suitable DVD DACĀ“s of a higher rate. (MPX Carriers)

Having settled on the samples per carrier, given the MPX sample rate, we use the RDSA bit rate to determine the number of carrier cycles required for each RDS bit. Of cause since there are 4 possible RDS carriers now the number of cycles must change for each sub-carrier. We further remember that we are dealing wth a modulated B.P.S.K so there must 4 possible amplitude shapes and two possible phase states. (See explication of the RDS v1.0 encoder)

Here comes the first problem.

It can be seen that the relationship between the sample rate 768KHz and the RDS bit rate 1.185KHz is not an integer, that means there is no exact synchonisation between the sample rate and the bit rate on a 250Hz cycle. (Solutions)


Adopting the solution 3 we can now move on to the base design. The same decoupled input-output is employed. One line up would be an ADAU1979 as the ADC, ADSP-21562 as the DSP and AD1955 for the DAC. Although the DSP could also be used as the human interface, any activity would be disruptive on the DSP flow so a seperate 32 bit flash based micro-controller would be better, allowing shared flash usage, serial (UCED), TCP/IP (Snmp), RTC for construction of the RDS frames eg: Coldfire. (Base Design)