Possible Solutions RDS v2.0

Solution 1

The simplest solution is to increase the cycle time to 0.5Hz = 2sec. The problem is the storage space require, since there will now be 384K samples per carrier and a rolling 0.5sec of RDS frames stored. The carriers go into flash, so should not be a problem but the RDS has to be dynamic and in RAM. Does the DSP have enough space? the ADSP215x does.

Solution 2

Stay with the 250Hz = 4mSec cycle and fit the RDS frames over, say a 5sec, as best as possible, this will result in a glitch every 5Sec. Since the RDS protocol is very rugged and easily rides such short glitches there will be no problem of transmssion. However inserting the time signal will be a bit tricky since the accurancy has to be maintained with 100mSec.

Solution 3

Similar to solution 2 but using interpolation and decimation to minimise the glitch. We observe that with a sample rate of 576KHz (3 x 192K) a RDS bit will require 485 samples with a difference of a mere 100nSec. So we split the the 100nSec difference between ajacent bits, producing a glitch well out side the RDS band, in fact out the MPX band.

Using this approach we sample the audio at 48K, 96K or 192K and interpolate (x12, x6, x3) to 576K, do the modulation, add RDS, then decimate to 192K for the output DAC. Although the same design philosphy is used as the original encoder, all the filters would have to be redone for anything other than the original 48K audio sample rate. For a 48K sample rate the 1:12 interpolation would not be done directly a 3:2:2 sequence would be better.

Now each symbol (modulated bit) occupies 485 samples with a 50nSec offset from zero crossing. There are 4 amplitude states and two phase state, so each 32bit long word can take 4 x 8bit amplitude values. and 2 long words for the 8 sysmbol states. Thus a mere 1152 long words are required to define all the symbol states per carrier.

The self same is used for each of the 4 RDS carriers as required.

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