Essentially a CPU (with ADC), a DAC and a number of glue components. The emphasis is on low cost hence the choice of a classic CPU rather than a DSP. Though a better choice nowadays would be the mixed core devices where a classical CISC CPU is combined with a DSP.
The essential components are the CPU, ADC and DAC. The ADC is incorporated into the CPU choosen so there are only two main components, the CPU and DAC. Level conditioning output filtering, serial port interface are auxiliary to these two core components.
The CPU is the Freescale MC9S12XE100, choosen because the CPU has two cores, a CISC core for general activities and a 100MHz RISC core dedicated to servicing the RDS data stream to the DAC. The CPU incorporates an ADC, serial port, integral flash memory, 64K RAM. This RAM is important so that there is sufficient space for the large data arrays required and allow the RDS RISC engine to run at maximum speed (100MHz) in RAM.
Only an 8 bit DAC is required but a 10bit parallel input DAC (Analog Device AD7533) was choosen for speed, pricing and availability. The output is a Bipolar 4 quadrant multiplier so the RDS can be produced without further level translation.
The other elements are a band pass filter to remove the DAC alias and noise, a level conditioner to convert the 19KHz pilot reference into a unipolar signal and a serial port interface.
The serial port is used for configuration of the RDS parameters (eq: PI) and change the dynamic information such as RT (Rich Text), TA (Traffic information). Although RS232 levels are used and the communication is asynchronous a specific protocol UECD (Universal Encoder Communication Data) is used to communicate with the RDS encoder. This protocol is common for all compliant encoders so the same control application can be used for RDS encoder from different manufactures.