The RDS generator is piece of equipment commonly used in FM Broadcast installations to produce a RDS sub-carrier with the stereo MPX signal. The RDS signal provides the radio receiver with a variety of information, the station call sign, program information, news flash, alternative station frequencies when on the move. Also broadcaster can use a user defined channel to send control information to a remote site, eg: program source switching.
In essence the RDS signal provides information to the receiver. This information is broken down into features, some compulsary (eg: PI program identification) and others optional. There is now a new RDS version v2.0 that provides enhanced features.
The RDS modulation is BPSK (Bi-phase shifted keyed) on a 57KHz carrier. The carrier is phase locked to the 19KHz pilot of a stereo MPX signal. The classical way of doing this is quite complicated with the need of a raised cosine shaping filter.
There is an alternative way (employed here) that allows a simple low cost RDS encoder to be made. Using a DAC (Digital Analogue Convertor) we can directly synthesise the RDS modulation, eliminating the need for a raised cosine filter and modulator functions. A low pass anti-aliasing filter is still required but can be very simple.
The resultant RDS BPSK modulation only has 4 possible symbol formats and 2 phases. The bit duration is known so the modulation can be divided in to a sequence of pre-calculated symbols. The symbol samples are fed to the DAC to produce the required modulation waveform.
The RDS modulation carried of 57KHz has to be phase locked to the 19KHz pilot of the MPX signal. This is a requirement since BPSK modulation does not transmit the carrier in order to save power, increase efficiency. In order for the demodulator/decoder to extract the RDS information the 19KHz pilot is used by the receiver to re-generate the 57KHz carrier and thereby extract the correct phase information.
This RDS generator design is intended for parallel operation so a clean 19KHz pilot is available. The RDS generator CPU uses uses an ADC to sample the pilot and lock an internal timer using a SDDPLL (Software defined digital phase lock loop). This internal reference maintains the symbol modulator in lock with the pilot reference.
The software is split into two parts as defined by the CPU architecture.(Freescale MC9S12XE). The RISC core is used for phase locking and sending the symbol data samples to the DAC. The CISC core is used for overhead handling, formatting the symbol array given the RDS data stream, generating the RDS data stream in the first place based upon a transmission cycle format. Interaction with the user via a serial port.
As CPU the Freescale MC9S12XE family is choosen. This is a dual core 16 bit micro-processor, a 50MHz CISC core + 100MHz RISC core + ADC + serial port. Use of two independent cores connected via a shared memory means the RISC engine can be dedicated to high speed programming of the DAC without interrupts breaking the data flow. Whereas the CISC core handles all the interrupts and handles the user interface.
RDS equipment control communication is based upon the UECP (Universal Encoder Communication Protocol) protocol. This enables a single application to access different types RDS encoders.
The RDS is configured and controlled by the standard serial UECP, so any UECP conformant application can be used to setup the standard RDS features. However since the RDS generator can also be used for manufacture dependent features, this implies a manufacture dependent variant of the application. here we look at such an application using C# NET, though I will not be going into detail of any manufacture specific features. The option is there.
The RDS-Forum (Geneva / CH) decided at its annual meeting (8-9 June 2015) in Glion/Montreux to bring the new standard RDS2 on the way. The standard combines with NRSC offering to create a unified platform for FM broadcasting data services WORLDWIDE.