Looking at how to Phase Lock to the Pilot
A example of a software DPLL
A mechanism is required to phase lock the RDS signal to the MPX pilot reference, though in some cases a Π/2 is better.
A software defined digital phase lock loop
The software defined digital phase locked loop is based upon a 32 bit shift register. There are 18 samples at 342KHz per 19KHz pilot cycle. So centered on the -ve to +ve zero crossing of the pilot, the shift register contains more than one cycle and is centred between bit 15 and bit 16.
The incoming 19KHz pilot reference is zero centered so a level comparision is made to generate a '1' for +ve and '0' otherwise. These bits are clocked into the shift register at the nominal 342KHz sample rate. Every 32 bits a comparision is made with the 0xFE00FF80 double word if all the bits coincide the loop is locked and no change is made to the 342KHz sample clock. In case of a difference the timer used for the sample clock is either decreased or increased.
The incremental time change is small. The nominal count for 342KHz = 2.92μSec is 146, so an incremental change of 1 is ࢥ0.02μSec
The self same timer is used to time the selection of the symbol samples for output to the DAC, thus constructing the modulated RDS data stream.