There are two software designs to be considered, one for the CISC engine and the other for the RISC engine.
Looking inside the CPU we see the following software setup:
The RISC engine loops continuously in an endless loop, taking the symbol information from the common memory shared between the RISC and CISC engines and generatiing the sample information for output to the DAC. The RISC engine is synchronised to the MPX pilot signal using a software PLL thus the DAC is programmed with level values at a locked sample rate. The symbol storage format, the DAC sample format and SDPLL method have been explained previously.
On the other hand the CISC engine only triggers on demand, making any changes, as required, to the data stored in the common RAM.
Thus one CPU runs synchronously (RISC) and the other asynchronously (CISC)