RDS Software Split Page

Split the RDS Software

The microprocessor has two CPU cores, one is a CISC and the other is a RISC. The user interface uses the CISC and the RDS generator machine in the RISC. The software diagram shown previously shows how this split is achieved. Here we look at the split in a little more detail


The CISC core runs slower than the RISC core but is more flexible, has more memory, a much bigger instruction set, handles flash and serial ports more efficiently. So here we have all the interface software, between the outside work on the serial port and the RISC engine doing all the hard boring work.

The CISC Core

As the CISC and RISC engines run independently all the data input can occur asynchronously since only the CISC part is involved. Only when any changes are concluded and saved to flash is a dataset change over invoked.

It is common nowadays to use SNMP or web to control devices such as the RDS device. This is easily achieved by adding on an Ethernet to serial convertor, of which there are many on the market. In both cases the web push or SNMP to UECP conversion would be done in the convertor. This seems to be something implicit in the new V2.0 specification in that the data rates involved are much higher.


Starting with the fact that the shared memory has been filled with one or more data sets that define the information that is to be sent to DAC. This the final shaped symbol to be transmitted. Since there only 8 pre-defined symbols that we can send from the RDS modulator, all the samples can be pre-stored in RAM (for fast access), so the modulator only needs to look up the symbol, emit the symbol samples collect the next symbol ad-infinitum.

Of cause the modulator cannot free run, that is where the SDPLL comes in to synchronise the modulator to the MPX pilot signal. Thus we synchronise to pilot, get a symbol, emit the symbol, wait for the next synchronisation point. The samples are paced by a sample oscillator that is brought into sync at every synchronisation point.

The RISC Core

The MCU used here does not need to be used (it just happened to be around at design time), in the main the code is MCU independent (Timers depend upon the MCU). If a faster MCU is used the sample rate can be increased, allowing for more precise definition of the modulation samples and reducing filtering requirements. Watchdog's and other safety measures also need adding on.

If a more feature rich approach is required, the same symbolic modulation approach can be used with a DSP. There are now commercial DSP with ADC, DAC, Flash and RAM, Ethernet port included. Thus allowing a RDS generator with very low component count to be constructed and SNMP control instead of UECP (though one could embed the UECP in SNMP frames).