Stereo Block Diagram Page
The stereo generator block diagram.
Here we describe the basic block diagram of the stereo encoder to show the asynchronous signal flow. Click on each block for more details.
Following the clock signal flow we see the master clock is 24.756MHz The accuracy of this master clock determines the pilot frequency, which must be 19KHz ±1Hz. The DAC uses the same clock signal but is driven as an external serial source, so the output signal flow is synchronised to the input signal sampling rate. Likewise the DSP runs of the master clock so all the internal timing to the DSP is also synchronised to to the same clock.
The DSP processing time is variable for each sample so the output samples are buffered, but extracted synchonously to the DAC.
The analogue to digital convertor(ADC)
The ADC is responsable for conversion of the left/right analogue audio channels into a serial data stream. A 12.288MHz clock is used to sample each channel in parallel at 48KHz. This is converted a serial stream of two 32 bit frames of which 24 bits are active as the conversion sample. The serial stream uses 3 wires, the bit clock, the data stream and a frame clock. The frame clock is used for synchronisation and left/right channel discrimination.
The DSP synchronises with the frame clock on one of the flanks. The ADC serial stream decides the flank sense to be used. The flank + flank sense triggers the DSP to accept the sample pair. This action triggers the whole of the MPX generation process.
The asynchronous digital receiver
The AES/EBU siganl is passed through an asynchronous digital receiver in order to isolate the external digital stream clock from the internal clock of the encoder. The digital stream can be of professional or consumer level from a mixer console or radio link. Thus isolation of the encoder master clock from external stream clock is required to avoid possible dropouts.
The digital signal processor (DSP)
The DSP must be sufficiently powerfull to completely process the incoming left/right channels to a MPX with margin to add a RDS modulation in the time between 2 analogue samples. At 48KHz sampling this is 20.83μSec. A SIMD (single instruction multiple data) DSP is choosen since this allows both incoming channels to be processed in parallel, all the filters, compression etc is done in paralle, leaving only the MPX construction and interpolation to be done in single data mode.
The digital to analogue convertor (DAC)
This is an stereo digital to analogue converter as commonly used in DVD sets. Instead of two analogue streams a MPX and pilot signal stream is generated. The 192KHz sampling rate allows MPX and RDS regeneration. Any possible SCA signals would normally be added externally.
Due to the 192KHz sampling rate there is a slight rolloff of the MPX response (see data sheet). This along with the MPX filter rolloff is compensated for in the DSP interpolation filter by incorporating a slightly up lift compensation.
The MPX output filter
This is a very important filter. Combined with the output interpolation filter incorporated in the DSP, the amplitude correction filter for the DAC rolloff, these three filters determine the characteristics of the MPX signal. To achieve a good crosstalk specification. If the required specification is -60db between main channels the a filter better than ±0.1db and ±0.1° is required.
The filter is a 6th order active Bessel with an amplitude adjustment for production trimming of the channel crosstalk. A buffer is used as the output driver with an optional isolating capacitor. A trimmer sets the final output level
The Pilot output filter
This is any type of bandpass filter, resonant at the 19KHz pilot frequency. For accurate reference purposes this signal should be phase synchonised with the pilot signal in the MPX output, so don't forget to includes both amplitude and phase adjustments to the filter.
The clock generator
The crystal controller master clock at 24.756MHz is used to synchronise the whole of the stereo generator. The accuracy of this clock with time and temperature determines the accuracy of the pilot signal. This clock is divided down by a synchronous divider to produce a bit clock for both the ADC and DAC. A frame reference signal is also produced for the output MPX syncronisation through the DAC.